Analog Design Engineer, Principal

Analog Design Engineer, Principal Locations: Pavia, Italy Time Type: Full time Posted on: Posted 2 Days Ago Job Requisition ID: 2402275 About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Central Engineering-Optical PHY (CE-OPHY) team designs high-speed and optical transceivers for communication infrastructure in long-haul, metro, and datacenters. We address the bandwidth, capacity, and power issues faced by cloud computing and mega data centers that power the social media giant platforms. Our innovative approaches have resulted in the company’s products being first to market in many key areas, developing the most advanced chips and subsystems solutions to address the ever-increasing demand for higher data rates driven by video-on-demand, gaming, and other real-time data streams. We are seeking talented individuals to work on solving technical challenges with the most outstanding group of collaborators in the industry. Join our team of experts and make a difference in an exciting career opportunity. As a member of a dynamic CE-OPHY team, the candidate will be responsible for designing circuits used for high-speed optical transceivers. The member will have an opportunity to work in deep submicron process and collaborate with the team on next-gen high-speed optical transceivers. What You Can Expect As a Principal Analog Design Engineer in the CE-OPHY team, you will be pivotal in developing multi-GHz analog or DSP-based transceivers in advanced CMOS nodes (3 nm and beyond). Key responsibilities include: Analyzing block specifications and selecting optimal topologies. Designing analog circuits at the transistor level. Supervising layout activities, providing guidelines, and conducting post-layout verifications. Modeling blocks and validating performance models. Collaborating with cross-functional teams to refine and improve design solutions. Designing entire analog macros or IPs for next-gen transceivers. Participating in cross-functional meetings to ensure alignment across teams. Training and mentoring junior design engineers. What We're Looking For Master’s degree in electrical engineering or related field with 10 years of experience, OR PhD in Electrical Engineering or related field with 7 years of experience. Proven expertise in end-to-end IC design, from architecture definition to lab characterization. Strong background in analog design, ideally in the multi-GHz range. Proficiency in analog custom layout and supervision. Skilled in EDA CAD tools, IC performance measurement, and debugging. Direct experience in one or more of the following: Multi-Gbps electrical SerDes or electro-optical transceivers. Advanced CMOS nodes, including FinFET. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. J-18808-Ljbffr

Location: Provincia di Pavia, IT

Posted Date: 11/9/2024