RHESO.TECH
Senior DFT engineer (W/M)
Job Location
Paris, France
Job Description
Senior DFT Engineer (W/M)
* Contract Type: Full-time (CDI)
* Location: Paris
* Ref: 1691
* Contact: ******************
Recruiting Company:
French fabless semiconductor manufacturer specialized in the design and marketing of highly integrated, mixed-signal semiconductor products for markets demanding wideband and low power analog-to-digital, digital-to-analog conversion.
Role:
The Design Team is looking for a dynamic and highly motivated senior DFT engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.
The candidate will drive and execute the definition and implementation of DFT in the chip.
in closed relationship with the physical implementation as well industrialization teams.
Responsibilities:
* Lead DFT architecture and DFT implementation for a complex SOC in advanced sub-20nm CMOS process.
* Develop and execute DFT flow, including HW DFT insertion, test vector generation, validation.
* Analyze digital DFT metrics and solutions considering DFT requirements: test time, yield, default rate.
* Advise digital design engineers on creating testable functional modules.
* Integrate DFT seamlessly with RTL design and physical implementation teams without SOC performance impact.
* Define optimum DFT solutions with the industrialization team, provide ATPG test vectors for production testing.
* Teamwork to design a state-of-the-art SOC, write documentation under QA policy, participate in design reviews.
Requirements:
* You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years hands-on DFT implementation experience in complex digital and/or SOC circuits and solid knowledge in RTL design.
* You command scripting languages like TCL, Perl, Python (as well as ATPG, BIST, ECC, Redundancy).
* You have hands-on experience with ASIC test methods and on silicium physical and electrical defects.
* You strongly understanding memory tests, logic tests (boundary scan, ATPG), JTAG (IEEE1149.1, IEEE1149.3) .
* Your plus: experience with Cadence DFT design flow, large designs with advanced sub-22nm CMOS technologies.
* You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, communicate fluently in oral and written English.
Education:
BAC+5, Master's Degree
RHESO.TECH, a specialized recruitment agency
https://www.rheso.tech/
Key words: DFT, Design, SOC, CMOS, ASIC, RTL, Cadence, Transceiver, Chip
Location: Paris, FR
Posted Date: 11/16/2024
* Contract Type: Full-time (CDI)
* Location: Paris
* Ref: 1691
* Contact: ******************
Recruiting Company:
French fabless semiconductor manufacturer specialized in the design and marketing of highly integrated, mixed-signal semiconductor products for markets demanding wideband and low power analog-to-digital, digital-to-analog conversion.
Role:
The Design Team is looking for a dynamic and highly motivated senior DFT engineer who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.
The candidate will drive and execute the definition and implementation of DFT in the chip.
in closed relationship with the physical implementation as well industrialization teams.
Responsibilities:
* Lead DFT architecture and DFT implementation for a complex SOC in advanced sub-20nm CMOS process.
* Develop and execute DFT flow, including HW DFT insertion, test vector generation, validation.
* Analyze digital DFT metrics and solutions considering DFT requirements: test time, yield, default rate.
* Advise digital design engineers on creating testable functional modules.
* Integrate DFT seamlessly with RTL design and physical implementation teams without SOC performance impact.
* Define optimum DFT solutions with the industrialization team, provide ATPG test vectors for production testing.
* Teamwork to design a state-of-the-art SOC, write documentation under QA policy, participate in design reviews.
Requirements:
* You hold an MSc or PhD in Electrical Engineering or equivalent, with over 10 years hands-on DFT implementation experience in complex digital and/or SOC circuits and solid knowledge in RTL design.
* You command scripting languages like TCL, Perl, Python (as well as ATPG, BIST, ECC, Redundancy).
* You have hands-on experience with ASIC test methods and on silicium physical and electrical defects.
* You strongly understanding memory tests, logic tests (boundary scan, ATPG), JTAG (IEEE1149.1, IEEE1149.3) .
* Your plus: experience with Cadence DFT design flow, large designs with advanced sub-22nm CMOS technologies.
* You demonstrate analytical and problem-solving skills, are a team player with a critical attitude and sense of initiative, communicate fluently in oral and written English.
Education:
BAC+5, Master's Degree
RHESO.TECH, a specialized recruitment agency
https://www.rheso.tech/
Key words: DFT, Design, SOC, CMOS, ASIC, RTL, Cadence, Transceiver, Chip
Location: Paris, FR
Posted Date: 11/16/2024
Contact Information
| Contact | Human Resources RHESO.TECH |
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