Mixed Verification Engineer

OUR STORY At ST, we believe in the power of technology to drive innovation and make a positive impact on people, business, and society. We are a global semiconductor company, and our advanced technology & chips form the hidden part of the world we live in today. When you join ST, you will be part of a global business of more than 115 nationalities and present in 40 countries, 50,000, diverse and dedicated creators & makers of technology around the world Developing technologies takes more than talent: it takes amazing people who understand collaboration and respect. People with passion and desire to disrupt the status quo, push boundaries and drive innovation – whilst unlocking your own potential. Working at ST means innovating for a future that we want to make smarter, greener, in a responsible and sustainable way. Our technology starts with you. Join us and start the future YOUR ROLE The position is aimed at a Mixed Signal Verification Engineer with previous experience in top-level analog simulations of ASIC. The preferred seniority is 3 to 5 years of experience. The candidate will be placed in the Mixed Verification team of the MEMS group and will have the possibility to follow all the ASIC verification process from specification definition up to final product industrialization. He/She follows the ASIC verification from specification definition up to silicon release. The level of autonomy and responsibility will be evaluated during the selection process. He/She will interact directly with the other verification engineers and the design team during the development phase and may be directly involved in silicon debug. YOUR SKILLS & EXPERIENCES - Master's degree in electronic engineering or similar - 3-5 years of experience in a similar position - Background in top-level analog simulations - Experience in analog modeling generation starting from ASIC specification - Experience in analog modeling integration in mixed and/or digital testbenches - Basic knowledge of VHDL and Verilog - Knowledge of System Verilog Assertion on Analog Signals is considered a plus - Universal Verification Methodology, System Verilog Assertions, Python scripts, Tcl scripts are considered a plus We encourage candidates who may not meet every single requirement to apply, as we appreciate diverse perspectives and provide opportunities for growth and learning. Diversity, Equity and Inclusion (DEI) is part of our company culture. Our DEI vision is, “At ST, you can be the true version of yourself.” We value all employee contributions and have zero tolerance for any kind of discrimination. Joining us is also about a greater work-life balance and a workplace with equal opportunities. Dedicated Employee Resource Groups for women and LGBTQIA, hybrid work arrangements are amongst the many DEI & Sustainability initiatives that make us a great place to evolve your career. To discover more, visit st.com/careers J-18808-Ljbffr

Location: emilia-romagna, IT

Posted Date: 11/24/2024