GLS Verification Engineer

GLS Verification Exp 6- 12 years - Verify and debug low-power design - Debug SDF Back Annotated Gate Simulations - Collaborate with cross-functional teams to define and execute gate-level simulation test plans. - Develop and implement gate-level simulation strategies for complex digital designs. - Conduct gate-level simulations to verify the functionality and performance of digital designs. - Work closely with design and verification teams to identify and resolve issues at the gate level. - Utilize your expertise in SV and UVM to optimize and enhance the gate-level simulation process. - Ensure compliance with industry standards and best practices in gate-level simulation. - Develop a comprehensive GLS methodology for the CPU - Perform gate-level simulations to verify the functionality, performance, and timing of CPU designs. - Develop and execute comprehensive test plans for gate-level simulations. - Collaborate with RTL design, verification, and physical design teams to identify and resolve simulation issues. - Analyze simulation results, debug failures, and propose design improvements. - Ensure thorough coverage and validation of all critical paths and corner cases. - Automate simulation workflows to enhance efficiency and reproducibility. - Assist in the development and maintenance of simulation environments and tools. - Document simulation methodologies, results, and best practices. - Understanding of industry-standard protocols and interfaces - Familiarity with static timing analysis (STA) and power analysis. (ref:hirist.tech)

Location: hyderabad, IN

Posted Date: 11/26/2024