DFT Engineer - SoC Architecture

Experience : 6-15 yrs. Location : Bangalore. In your new role you will : - Responsible for SoC DFT Architecture debug of SoC/Full Chip. - Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. - Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. - Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. - Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. - Hands on experience in analysis and debug of above-mentioned test domains. - Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out. You are best equipped for this task if you have : - 6 years of in DFT implementation, verification and post silicon debug areas. - ASIC flow understanding. - Experienced in LEC, CLP, power analysis flow is preferred. - The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. - In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. - The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. - Scripting skills such as PERL/TCL/Python are preferred. (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 11/28/2024