Principal Layout Engineer

Onsemi is seeking a Principal Analog Layout Engineer for New Product Development in Power Management to join our growing team in Milano (Italy). This group is responsible for the development of Power Management products, including Multiphase controllers and Dr. MOS for Cloud and Computing applications. In this role, you will focus on the following: Mentor junior Analog IC layout engineers to produce high-quality layouts for complex AMS blocks (voltage regulators, bandgap, current sense-amp, amplifier, etc.). Drive critical floor-planning decisions. Have a good understanding of full custom layout analog blocks in BCD/CMOS technologies, physical verification flow, IP/chip floor planning, placement, creating mask databases for tapeout, and tapeout procedures. Contribute to area estimation and optimization processes, floor planning, power routing, shielding, physical verification (DRC, ERC, LVS, ESD, etc.), as well as power analysis (EM / IR-Drop) and tape-out layout sign-off. Interact with synthesis, STA, and top-level responsible people within the product development team, as well as with local project managers. Actively seek out opportunities to work with cross-functional teams (Chip team, Tech, CAD). Produce IP layout that meets quality standards for both industrial and automotive applications. Understand project goals, develop a realistic IP layout schedule, and provide full clarity to the team on the goals and objectives. Develop scripts and methods for design automation to reduce cycle time. J-18808-Ljbffr

Location: lombardia, IT

Posted Date: 11/28/2024