Lead Physical Design Engineer - STA/Timing Closure

About Company : Hiring for one of the leading and fastest growing company, which provides a wide range of services to businesses of all sizes. Specialized in developing mobile applications, full-stack development, and scalable backend development. We specialize in semiconductor, ASIC Design services, Physical design, ASIC Verification, and Physical Verification Experience : 10 years Location : Bangalore Work type : Permanent Work Mode : WFO Job Description : Key Qualification : Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies. Expert in STA and methodologies for timing closure, and have a deep understanding of noise, crosstalk, and OCV effects, among others. Familiar with circuit modeling Strong programming skills with Perl and TCL. Experience with large design STA and Timing Closure. Good communicator who can accurately describe issues, propose solutions, and drive them through completion. Work with design teams to understand and debug constraints, facilitate logic changes to improve timing. Work with Physical Design team, highlighting issues and best practices. Create and maintain scripts and methodologies for analysis and runs. Create documentation and help with guidelines/specs Experience in Block/SOC level PD Implementation flow. Experience in Netlist to GDSII / PD / Implementation flow / PnR / APR Should have experience in Low power designing. Experience in Floor planning, Power planning, Placement, CTS, Routing, Extraction, DFM. Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing and Sign Off ( STA, PV, IR/EM) Experience in ECO implementation Should have hands on experience in PnR tools Synopsys ICC II/ Cadence Innovus etc Should possess good Leadership Skill Should be with Go-getter attitude Must have good communication & problem-solving skills (ref:hirist.tech)

Location: bangalore, IN

Posted Date: 11/29/2024